1. Field of the Invention
The invention relates to the field of manufacture of microelectronics fabrications. More particularly, the invention relates to the field of pattern formation by subtractive etching of microelectronics layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are comprised generally of layers of microelectronics materials formed upon microelectronics substrates. Many of the microelectronics layers are formed into patterns in order to embody their functions within the microelectronics fabrications. The materials employed may be microelectronics conductor, microelectronics semiconductor and microelectronics dielectric materials.
Of particular interest for microelectronics fabrication are patterned microelectronics dielectric layers formed from undoped or doped silicon containing dielectric materials. It is commonly required to employ patterns wherein there are very fine features such as contact via holes, fine lines and other features with high aspect ratios in the dielectric layer. Such patterns may be formed employing photolithographic methods and materials to form etching mask layers over the dielectric layer and subtractive etching of the dielectric layer through the etch mask. Because of the need for ever smaller dimensions, plasma activated gas phase reactive etching is widely employed as the subtractive etching method.
Although satisfactory for serving the needs of microelectronics fabrication in general, such plasma activated gas phase reactive etching methods are not without problems. For instance, it is sometimes difficult to maximize for a given etch method the etch rate and/or dimensional resolution of a given silicon containing material while still retaining the large discrimination of high etch rate for the material being etched and low etch rate for the etch mask material. Likewise, it is often difficult to maintain the high resolution etching capability of the reactive etching method equally well for more than one silicon containing dielectric material.
It is thus towards the goal of providing an etch method with high discrimination between the etched pattern material and the etch mask material as well as high resolution etching capability that the present invention is directed.
Various methods have been disclosed to provide etch rate discrimination and resolution of very fine etched features in plasma activated subtractive etching of silicon containing dielectric materials.
For example, Araki et al., in U.S. Pat. No. 5,770,098, disclose an etching method with high etching selectivity for silicon oxide layers which prevents formation of fence defects in the etched pattern. The method employs a carbon monoxide oxidizing gas and a reactive gas consisting of Group IV and Group VII elements but not containing hydrogen in a plasma activated process in a reactor chamber.
Desirable in the art of microelectronics fabrication are additional methods for etching high resolution patterns at high rates with discrimination between high pattern etching rates and low mask etching in silicon containing dielectric layers employing plasma activated reactive etching gases.
It is towards these goals that the present invention is generally and more specifically directed.
A first object of the present invention is to provide a method for etching a pattern in a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention where the pattern is subtractively etched employing a plasma activated reactive gas mixture.
A third object of the present invention is to provide a method in accord with the first object of the present invention and/or the second object of the present invention where the relative etch rates of material layers and etch rate selectivity of the etching process is controlled by the gas composition
A fourth object of the present invention is to provide in accord with the first object of the present invention, the second object of the present invention and the third object of the present invention where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for etching within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication a pattern employing a plasma activated reactive gas mixture with etch rate, aspect ratio and etch rate ratio controlled by gas composition. To practice the invention, there is provided a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication. There is placed the substrate within a reactor chamber containing electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. Nitrogen and inert carrier gases may also be included, but excluded are oxidizing gases containing carbon and oxygen. There is then supplied high frequency electrical energy to the electrodes to bring about a plasma activated reactive gas etching environment, with the conditions chosen to optimize the etching reaction rate and etching rate selectivity of the etching process for particular silicon containing dielectric layers and etch mask layers.
The present invention provides a method for selective etching of a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication. The etch rate and etch rate selectivity for the particular silicon containing dielectric material and etch mask layer material may be chosen by control of the etching gas composition.
The present invention provides a reactive gas which upon plasma activation subtractively etches silicon containing dielectric materials. The reactive gas employs an oxidizing gas as well as reactive gases and carrier gases, but the precise control and selectivity of etch rates are better obtained with exclusion of oxidizing gases containing carbon and oxygen, as such gases are observed to limit the etch rate range of silicon containing dielectric materials as their composition varies.
The method of the present invention may be employed to form a pattern within a silicon containing dielectric layer formed upon a substrate employed within a microelectronics fabrication which may be chosen from the group including but not limited to integrated circuit microelectronics fabrications, charge coupled microelectronics fabrications, solar cell microelectronics fabrications, radiation emitting microelectronics fabrications, optoelectronics display microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The method of the present invention employs methods and materials which are known in the art of microelectronics fabrication, but in a novel order and sequence. Therefore the method of the present invention is readily commercially implemented.